Poster Sessions | Taiwan and Japan Conference on Circuits and Systems 2025

Regarding the poster sessions, uploading your poster file is not required. Please print your poster in advance and bring it with you to the conference. Display your poster in the designated poster area before your oral presentation begins. Speakers will first deliver their oral short presentations in the Wah Lee Hall. After all presentations have concluded, all participants will proceed to the poster area to view the posters. Please remove your poster at the conclusion of your poster session. Authors are responsible for printing, bringing, and displaying their posters, as the organizers will not provide poster printing or installation services. The poster should have a portrait (=vertical) orientation, NOT landscape. The poster dimensions should be equal to A0 size (841mm in width and 1189mm in height). (Read more: about the Poster Template)

Note 1: In the poster area, each display board is marked with a Session ID. Please find the board where the number inside the parentheses matches your submission ID and hang your poster there.

Note 2: We encourage all authors to prepare their best work, as all posters will be automatically entered into the Best Poster Award Competition.

Poster Sessions	Setup Time	Duration	Removal Time	Location
Poster Session 1 (August 28, 2025)	08:20-09:00	11:25-12:05	12:05-12:10	Posters Area
Poster Session 2 (August 28, 2025)	12:30-13:10	15:25-16:05	16:05-16:10	Posters Area
Poster Session 3 (August 29, 2025)	08:20-09:00	11:25-12:05	12:05-12:10	Posters Area

Session: Poster Session 1

Date： Thursday, August 28, 2025
Time： 11:25-12:05
Venue： Posters Area

Session ID	Title / Author / Affiliation
1.1 (5)	Modeling and Analysis of Gate and Power Loop Parasitics in GaN HEMT Double Pulse Test (DPT) Susmita Mistri¹, Chang – Ching Tu^2,3, and Hao Chung Kuo^1,2 ¹ Yang Ming Chiao Tung University, Taiwan ² Hon Hai Research Institute, Taiwan ³ National Central University, Taiwan
1.2 (2)	A high dynamic range CMOS image sensor based on an 8-bit two-step single-slope Analog-to-Digital Converter Ko-Chi Kuo, Hao-Jie Xiao, and Jia-En Hu National Sun Yat-sen University, Taiwan
1.3 (26)	A Bulk-Driven Low-Power CMOS TIA for 8 Gb/s Optical Communication Kensuke Mizutani, Shunsuke Imaeda, Yabutani Tsubasa, Daisuke Ito, and Makoto Nakamura Gifu University, Japan
1.4 (7)	One-Input-Five-Output Voltage-Mode Universal Biquad with High Input Impedance Using Three Current Conveyors Jiun-Wei Horng, Ting-Yu Hsiao, Fu-Hsiu Chen and Chang-Ming Wu Chung Yuan Christian University, Taiwan
1.5 (13)	A 88.6-dB SNDR Discrete-Time Delta-Sigma Modulator Using Two-Stage Floating Inverter Amplifiers in 180-nm CMOS Chun-Yang Chiu, and Yung-Hui Chung National Taiwan University of Science and Technology, Taiwan
1.6 (14)	A 10-bit 40-MS/s Capacitor-Swapping SAR ADC in 180nm CMOS Ying-Liang Li and Yung-Hui Chung National Taiwan University of Science and Technology, Taiwan
1.7 (29)	Design of Discrete Integrator Using Digital Circuits Soma Fukuta, Daisuke Mizushima, Norio Tsuda, and Keishiro Goshima Aichi Institute of Technology, Japan
1.8 (84)	Study on Improving the Slew Rate of Tracking A/D Converters Keiya Kanoh and Masahiro Sasaki Shibaura Institute of Technology, Japan
1.9 (4)	A 36-Gb/s 1.6-pJ/b PAM-3 Transmitter Leveraging Digital Logic Cells and 4-Tap FFE in 22-nm CMOS Ming-Xun Wang, Wei-Ting Lin, Yao-Chia Liu, and Philex Ming-Yan Fan National Cheng Kung University, Taiwan
1.10 (18)	A 0.9-3.6 Gb/s PVT Robust Ground Bounce Tolerant 1/3-Rate Low Power Bang-Bang CDR with ±12% Spread Spectrum Clock Modulation Depth for Laptop Sung Huang and Soon-Jyh Chang National Cheng Kung University, Taiwan
1.11 (23)	Low Power Harmonic Rejection Receiver With Passive Harmonic Recombination Technique Jhih-Hao Hong and Kuang-Wei Cheng National Cheng Kung University, Taiwan
1.12 (12)	CL-Concat: An Attention-Augmented Feature Fusion Module for Aerial Object Detection Haimin Yan^†, Xiangbo Kong^‡, Tomoyasu Shimada^†, and Hiroyuki Tomiyama^† ^† Ritsumeikan University, Japan ^‡ Toyama Prefectural University, Japan
1.13 (21)	Dynamic Obstacle Avoidance for Micro-Drones via Monocular Depth Estimation and Model Predictive Control Ryo Fujimoto^†, Tomoyasu Shimada^†, Xiangbo Kong^‡, and Hiroyuki Tomiyama^† ^† Ritsumeikan University, Japan ^‡ Toyama Prefectural University, Japan
1.14 (1)	Porting and Performance Optimization of a Lightweight CMS on Raspberry Pi Ting-Yun Cheng, Chia-Chi Chang National Changhua University of Education, Taiwan
1.15 (52)	Visualization of Waveform-Shaping Effects in Higher-Order FFEs Using Multi-Valued Multi-dimensional Symbol Mapping Yasushi Yuminaka, Ryou Andachi, Yosuke Iijima, and Haohao Zhang Gunma University, Japan National Institute of Technology (KOSEN), Oyama College, Japan
1.16 (8)	Weight-Aware and Reduced-Precision Architecture Designs for Low-Cost AI Accelerators Shyue-Kung Lu and Yu-Xian Huang National Taiwan University of Science and Technology, Taiwan
1.17 (19)	Efficient FPGA-Based Arbiter PUF Design with Placement Optimization Yu-Wen Cheng, Yi-Chen Li and Tong-Yu Hsieh National Sun Yat-sen University, Taiwan
1.18 (6)	Vector Processor with Variable Bit-Precision Yu-Hsuan Chen, Chu-Chun Chan, and Lih-Yih Chiou National Cheng Kung University, Taiwan
1.19 (10)	An Integrated FPGA Implementation of Complete GNN-Based Trajectory Reconstruction Yun-Chen Yang^, Hao-Chun Liang^, Hsuan-Wei Yu^, Bo-Cheng Lai^, Shih-Chieh Hsu^†, Mark Neubauer^‡, Santosh Parajuli^‡ ^* National Yang Ming Chiao Tung University, Hsinchu, Taiwan ^† University of Washington, USA ^‡ University of Illinois Urbana-Champaign, USA
1.20 (11)	An Automated Framework for Deep Learning Compilation and FPGA Accelerator Design Hsien-Chen Chiu and Bo-Cheng Lai National Yang Ming Chiao Tung University, Taiwan
1.21 (25)	Development of Autonomous UAV Systems with Enhanced Safety and Reliability via Local 5G Haohao Zhang, and Yasushi Yuminaka Gunma University, Japan
1.22 (16)	Pipeline Optimization Design and Implementation of Hardware Architecture for Multi-Head Self-Attention Mechanism in Large Language Model Acceleration Wen-Jia Yang, Chung-Bin Wu, and Chao-Ping Liu National Chung Hsing University, Taiwan
1.23 (9)	Design-for-Testability and Built-In Self-Test Techniques for Systolic Array-Based AI Accelerators Shyue-Kung Lu and Cheng-You Shi National Taiwan University of Science and Technology, Taiwan
1.24 (15)	Energy-Efficient ROI-Based Error Tolerance Evaluation for Object Detection in Video Streams Jun-Tsung Wu¹, Tong-Yu Hsieh¹, Hideyuki Ichihara², and Tomoo Inoue² ¹ National Sun Yat-sen University, Taiwan ² Hiroshima City University, Japan
1.25 (17)	Aging-Aware Timing Resilience Framework for Systolic Array-Based AI Accelerators Tsung-Chun Chen, Wei-Ji Chao, Chu-Cheng Chen and Tong-Yu Hsieh National Sun Yat-sen University, Taiwan
1.26 (33)	Simulated Annealing-Based Placement and Routing Method for Non-Island-Style eFPGA Yumi Iseki, Masahiro Iida, and Kenshu Seto Kumamoto University, Japan
1.27 (30)	Replacement of Parametric Resonant Circuit with FPGA Kota Sukimoto¹, Norio Tuda¹, Yushi Ichihara², and Keishiro Goshima¹ ¹ Aichi Institute of Technology, Japan ² Quantum Information Corporation, Japan
1.28 (42)	Solving SAT Problem with Quantum Annealing Remma Ukaku, Tomohisa Kawakami, and Hiroyuki Tomiyama Ritsumeikan University, Japan
1.29 (62)	Enabling Efficient Integer-Only Few-Shot Learning on Edge Devices Che-Juei Kuo, Chih-Hung Kuo, and Hao-Chun Chan National Cheng Kung University, Taiwan

Session: Poster Session 2

Date： Thursday, August 28, 2025
Time： 15:25-16:10
Venue： Posters Area

Session ID	Title / Author / Affiliation
2.1 (53)	Inverter-Based Regenerative Braking for PMSM Drives Using SVPWM and FOC Muhammad Rifqi Nur Sabilillah^{1, 2}, Hideo Pratama², Yao-Ching Hsieh², Rini Nur Hasanah¹, and Muhammad Aziz Muslim¹ ¹ Universitas Brawijaya, Indonesia ² National Sun Yat-sen University, Taiwan
2.2 (44)	Data-Driven Low-Permeability Transformer Modeling for High-Frequency Converter Design Wenying Xu, Hiroshi Osawa, Daisuke Miyagi, Ayano Komanaka, Kien Nguyen, and Hiroo Sekiya Chiba University, Japan
2.3 (78)	Active Gate Drive for Spike Current Suppression in Switched-Capacitor Converter Jia-Ming Zhang and Le-Ren Chang-Chien National Cheng Kung University, Taiwan
2.4 (40)	A 4.2–5.0 GHz LC VCO with Small Kvco Variation in 180-nm CMOS Yen-Chung Chiang and Tzu-Hsuan Tseng National Chung Hsing University, Taiwan
2.5 (35)	A 28-nm 10-bit 100MS/s 0.119mW SAR-ADC Using Associated Reverse Error-tolerant Capacitance Technique Hsiang-Yu Chuang¹, Yi-Te Yeh¹, Zhong-Wei Yu¹, and E Ray Hsieh² ¹ National Central University, Taiwan ² Yang Ming Chiao Tung University, Taiwan
2.6 (38)	A Single Channel 10-Bit 2.5-GS/s Pipelined ADC With Time-Assisted Residue Generation Jyun-Yi Ho and Soon-Jyh Chang National Cheng Kung University, Taiwan
2.7 (41)	A Single-channel 74dB-SNDR 80MHz-BW Pipelined Noise-Shaping SAR ADC Jing-Zhong Chen and Soon-Jyh Chang National Cheng Kung University, Taiwan
2.8 (47)	A 10-b 56-MS/s Calibration-Free SAR ADC Array for Touch Sensing Applications Chin-Wei Cheng and Soon-Jyh Chang National Cheng Kung University, Taiwan
2.9 (45)	INVESTIGATION OF BEHAVIOR OF CHAOTIC CIRCUITS WITH NONLINEAR COUPLING Takeru Tochigi, Kouhei Suzue, Yoko Uwate, and Yoshifumi Nishio Tokushima University, Japan
2.10 (31)	Efficient Neural Network Architecture Pruning via K-Means Clustering for Memory and Computation-Constrained Edge Devices You Jin Liu¹, Ke Yi Li¹, Bo Yi Wu¹, Yung Ching Chung¹, Yu Shan Chou¹, Chien Chang Chen¹, and E. Ray Hsieh² ¹ National Central University, Taiwan ² National Yang Ming Chiao Tung University, Taiwan
2.11 (71)	Clustering Based Aggregation for Large-Scale HVAC Systems Zhiyuan Lu, Dafang Zhao, Hiroki Nishikawa, Ittetsu Taniguchi, and Takao Onoye The University of Osaka, Japan
2.12 (43)	A Methodology for Selecting Approximate Adders and Multipliers in MAC Units to Optimize CNN Accelerator Efficiency Kuo-Hung Liao, Jun-Tsung Wu, Wei-Chen Liu, and Tong-Yu Hsieh National Sun Yat-sen University, Taiwan
2.13 (46)	Design and Implementation of a MobileNet-Based Hardware Accelerator for Deep Neural Networks Kuang-Hao Lin and Yi-Lin Chen National Formosa University, Taiwan
2.14 (27)	Efficient Design Circuit For Epoch–reduced Spiking Neural Network (SNN) Machine Learning Model Yen-Yu Li and Xin-Yu Shih National Sun Yat-sen University, Taiwan
2.15 (63)	Design and Implementation of a Quad-Core Multi-Stream SIMD RISC-V Processor Architecture Supporting SPMD Mechanism for Machine Learning Jih-Ching Chiu, Pin-Yao Chen, and Li-Ming Yang National Sun Yat-sen University, Taiwan
2.16 (55)	Design and Analysis of Configurable Near Memory-based GPGPU Platform Zhong-Kai Zheng, Hsiang-Hao Hsu, and Lih-Yih Chiou National Cheng Kung University, Taiwan
2.17 (86)	Precise Work Activity Classification Based on Machine Learning with Statistical Feature Sensed from Inertial-Measurement-Unit Assisted Ultrawideband Positioning I-Chyn Wey, Ting-Suo Yang, and Ching-Yu Chen Chang-Gung University, Taiwan
2.18 (58)	AES Hardware Design with Integrated Power Side-Channel Attack Countermeasures Chih-Yu Chen, Yueh-Tzu Huang, and Tong-Yu Hsieh National Sun Yat-sen University, Taiwan
2.19 (75)	An Instruction-Level Parallelism Techniques for the application in enhancing the Performance of a Processor Tin-Yao Kung and Hsin-Wen Ting National Kaohsiung University of Science and Technology, Taiwan
2.20 (3)	CPU Microarchitecture Optimization in Luna SoC Pei-Shan Hsiao, Yi-Teng Zhuang, and Chung-Ho Chen National Cheng Kung University, Taiwan
2.21 (82)	Enhancing the Efficiency of Parallel Inter-Chip Communication Bus via TSVs in 3D-Stacked LSI Systems Yuto Shiota, Masahiro Aoyagi, and Takeshi Ohkawa Kumamoto University, Japan
2.22 (65)	Thermal Images Lossless Compression Algorithm for IoT and Industry 4.0 Tzu-Ling Chang¹, Ya-Yun Huang², and Shih-Lun Chen¹ ¹ Chung Yuan Christian University, Taiwan ² National Cheng Kung University, Taiwan
2.23 (32)	Functional Test Generation for Detecting Safety-Critical Errors in AI Accelerators Ching-Hsin Hsu, Wei-Ji Chao, Rui-Lun Wu, and Tong-Yu Hsieh National Sun Yat-sen University, Taiwan
2.24 (24)	Performance Modeling of the UCIe 1.0 Protocol Yin-Yin Shen and Lih-Yih Chiou National Cheng Kung University, Taiwan
2.25 (39)	A Scalable Delay Modeling Framework for DCIM Circuit Yung-Chi Chia and Shih-Hsu Huang Chung Yuan Christian University, Taiwan
2.26 (28)	RITS: Real-world Raindrops Removal Image Training and Test Sets for Autonomous Driving Asami Oganna^†, Tomoyasu Shimada^†, Xiangbo Kong^‡, and Hiroyuki Tomiyama^† ^† Ritsumeikan University, Japan ^‡ Toyama Prefectural University, Japan
2.27 (48)	Efficient Monocular Depth Estimation Using Depthwise Separable Convolutions Genki Higashiuchi^†, Tomoyasu Shimada^†, Xiangbo Kong^‡, and Hiroyuki Tomiyama^† ^† Ritsumeikan University, Japan ^‡ Toyama Prefectural University, Japan
2.28 (36)	A 1.1 V-Programmable Metal-Fuse Technology With Current-Mode Programming and Program-Guarantee Technique in 28 nm CMOS Technology Chih-Hao Wang and Philex Fan National Cheng Kung University, Taiwan

Session: Poster Session 3

Date： Friday, August 29, 2025
Time： 11:25-12:10
Venue： Posters Area

Session ID	Title / Author / Affiliation
3.1 (57)	A 84dB-SNDR 25MHz-BW Noise-Shaping-Pipelined-SAR ADC with Direct Interstage Gain-Error-Shaping Chih-Fa Chung and Soon-Jyh Chang National Cheng Kung University, Taiwan
3.2 (77)	A 28-nm Int-Bit Modulation 400MS/s Flash-SAR ADC with +/-Voltage Detection for High-Speed CIM Applications Chih-Te Lee¹, Mao-Cheng Huang¹, Guan-Yan Lin¹, and E Ray Hsieh² ¹ National Central University, Taiwan ² National Yang Ming Chiao Tung University, Taiwan
3.3 (72)	Design and Analysis of a β-Multiplier Reference Circuit in 16-nm FinEFT Technology Tzung-Je Lee and Li-Yang Shih National Sun Yat-sen University, Taiwan
3.4 (73)	Design and Analysis of a Two-Stage Operational Amplifier Using gm/ID Methodology in 16-nm FinFET Technology Tzung-Je Lee and Yu-Kai Huang National Sun Yat-sen University, Taiwan
3.5 (81)	Development and Analysis of EMI model in SJ-DMOS for Flyback Converters Tzung-Je Lee and Teng-Tai Sun National Sun Yat-sen University, Taiwan
3.6 (20)	An Energy-Efficient SRAM-based CIM Circuit Design Zong-Han Li, Jing-Yang Lin, Zhao-Long Zheng, and Lih-Yih Chiou National Cheng Kung University, Taiwan
3.7 (85)	Synchronization in Scale-Free Networks of Chaotic Circuits with Power-Law Distributed Coupling Strengths Shota Katayama, Kazuki Yano, Yoko Uwate, and Yoshifumi Nishio Tokushima University, Japan
3.8 (67)	Temporal Switching and Nonlinear Dynamics in a Chaotic Circuit with a Memristor Taishi Segawa, Yoko Uwate, and Yoshifumi Nishio Tokushima University, Japan
3.9 (66)	Compact-LLaMA: Compressing and Inferencing LLaMA on the Edge Jun-An Chen, Jia-Hao Hu, Chi-Chang Lin, and Chih-Hung Kuo National Cheng Kung University, Taiwan
3.10 (56)	Design of an Energy Efficiency CIM-based Neural Network Accelerator for Inference and learning Tsung-Chi Chen, Hsuan-Yu Lin, and Lih-Yih Chiou National Cheng Kung University, Taiwan
3.11 (70)	Design and Performance Analysis of a Shape-Reconfigurable Systolic Array Accelerator Hao-Chen Hong, Chih-Hung Kuo, and Guan-Ying Chen National Cheng Kung University, Taiwan
3.12 (74)	Dynamic Bit Truncation Technique for AI Inference Accelerators Tzung-Je Lee and Jin-Shiuan Huang National Sun Yat-sen University, Taiwan
3.13 (60)	Design and Implementation of a Hardware Accelerator for the YOLO Machine Learning Model Jih-Ching Chiu, Yi-Chen Hsieh, and Qing-You Lin National Sun Yat-sen University, Taiwan
3.14 (22)	Maximally Compressed Approximate Communication Module for High-Efficiency CNN Inference Po-Kai Huang, Jun-Tsung Wu, Jun-Zhao Zhang, and Tong-Yu Hsieh National Sun Yat-sen University, Taiwan
3.15 (79)	A Study on Demodulation Improvement in Light-Trail-Based Image Sensor Communication via Intentional Image Blur Ayato Yamamoto¹, Wataru Tafusa¹, Daisuke Ito², and Shintaro Arai¹ ¹ Okayama University of Science, Japan ² Gifu University, Japan
3.16 (80)	Automated Insect Detection Platform Featuring Human–Machine Interaction and Multi-Scale CNN Recognition Song-Min Ke, Chang-Yu Wu, Chang-Yi Chu, Hoh-Siang Liao, Ying-Hsiu Hung, and Shin-Chi Lai National Formosa University, Taiwan
3.17 (61)	Design and Implementation of a Multimodal Intra and Inter Prediction Accelerator Jih-Ching Chiu, Chun-Yu Su, and Li-Ming Yang National Sun Yat-sen University, Taiwan
3.18 (59)	Real-Time Multi-lead ECG Monitoring with Denoising Autoencoder and Wireless Acquisition System Zheng-Rong Chen, Chien-Hong Lai, Shin-Yu Lin, and Shin-Chi Lai National Formosa University, Taiwan
3.19 (69)	Food Nutrition Answering System Based on Knowledge Graph Chin-An Kuo, Gwo Giun Chris Lee, Chu-Chun Yang, and Hsin-Yu Chao National Cheng Kung University, Taiwan
3.20 (83)	FMCW Radar-Based Heart Rate Estimation with Motion Artifact Suppression using CNN Autoencoder–Transformer Shang-Sian Wu, Szu-Ting Wang, and Shin-Chi Lai National Formosa University, Taiwan
3.21 (68)	A Lightweight Processor Recovery Mechanism against Fault-Injection Attacks Lin-Jing Kuo, Chia-Yuan Lu, Yi-Hsuan Pan, Wen-Wei Shih, and Jiun-Lang Huang National Taiwan University, Taiwan
3.22 (51)	Cyclic Time-to-Digital Converter Compiler for Accurate Clock Jitter Measurement Jin-Sheng Pan¹ and Shi-Yu Huang^{1, 2} ¹ National Tsing Hua University, Taiwan ² National Institutes of Applied Research (NIAR), Taiwan
3.23 (54)	Process Variation Resilient Time-to-Digital Converter for Clock Jitter Measurement Chih-Chia Hsu and Shi-Yu Huang National Tsing Hua University, Taiwan
3.24 (64)	Preventing Setup-Time Attacks in FSMs via Clock Skew Scheduling Chang-Jun Lin and Shih-Hsu Huang Chung Yuan Christian University, Taiwan
3.25 (49)	ELIF : Efficient LiDAR-Image Fusion for Accelerationg 3D Object Detection Yuto Sakai^†, Tomoyasu Shimada^†, Xiangbo Kong^‡, and Hiroyuki Tomiyama^† ^† Ritsumeikan University, Japan ^‡ Toyama Prefectural University, Japan
3.26 (37)	Fast Droplet Routing on MEDA Biochips through Splitting and Target-Guided Constraints Yuta Hamachiyo^†, Chiharu Shiro^{†, ‡}, Hiroki Nishikawa^§, Hiroyuki Tomiyama^†, and Shigeru Yamashita^† ^† Ritsumeikan University, Japan ^‡ WITZ Corporation, Japan ^§ The University of Osaka, Japan